Conventionally, a system in which a plurality of units (devices) access a memory unit has been employed. An arithmetic unit, such as a central processing unit (CPU) or the like, and an input/output unit generally called an “Input/Output” (IO) are some examples of access source units that access the memory unit.
A system controller is provided between the memory unit and the access source unit. The system controller locks a storing destination address in the memory unit in which a store access has occurred to perform exclusive control, so that data consistency may be maintained even in a case where there is a plurality of access source units. Furthermore, the system controller checks to see if there is cache data about a destination address of an access request, so that data coherency may be maintained, in a case where the access source unit, such as the CPU, having a cache, is coupled to the system controller.
Moreover, an information processing system has also been employed in which the memory unit and the access source unit are coupled to the system controller to form a system board and the plurality of such system boards are coupled with each other. As to the information processing system that includes the plurality of system boards, the system controller provided on each of the system boards communicates with each other to transfer access requests, so that each access source unit may access the memory unit within the same system board or may access the memory unit on the other system board.
To maintain the data consistency in the store accesses between the system boards, each of the system controllers reports on access generation status and/or cache status within the same system board with each other and performs a global snoop by which determination of status of accesses in an entire system is made.
When it is determined, based on the global snoop, that a memory unit may be in an accessible state, the system controller provided on the system board on which an access request has been generated locks a destination address of included in the access request and executes access processing.
In addition, as to the data cached by the CPU within the same system board, it is quite certain that neither a cache nor an access has been generated on the other system board. In consequence, a local snoop is performed by which determination is made whether or not the destination address of the access request generated in a system board is cached within the same system board. When it is determined, based on the local snoop, that the destination address is being cached within the same system board, the system controller accesses the memory unit without waiting for a determination result by the global snoop, so that faster processing may be achieved.
[Patent Document]
Japanese Laid-Open Patent Application No. Hei7-21077
[Patent Document]
Japanese Laid-Open Patent Application No. Sho58-107977
[Patent Document]
Japanese Laid-Open Patent Application No. Hei4-271450
[Patent Document]
Japanese Laid-Open Patent Application No. 2006-72509
In the configuration in which the plurality of system boards is coupled with each other, it has been typical that each system board includes a CPU thereon to improve its processing capability. However, thanks to the improved processing capability of CPUs in recent years, the other configuration is employed in which the CPUs are brought together on one system board and only input/output units (IOs) are provided, as the access source unit, on the other system boards.
In the configuration in which the CPUs are provided on two or more system boards, processing with the local snoop is possible by each system board when the CPU within the same system board gets a cache hit. However, there is a possibility that data is cached by the CPU on the other system board, in a cache miss within the same system board. Under such circumstances, for this reason, processing with the global snoop is performed in the cache miss within the same system board.
In the configuration where the CPUs are brought together on one system board, it is unnecessary to take the possibility into consideration that the data is being cached on the other board. However, in the above case, when a store access is made from the other board to the memory unit within the same system board, address locking is made at the system board that is a source of access. In consequence, the global snoop is performed to check the status of accesses to the memory unit within the same system board.